This application claims the benefit of Japanese Patent Application No. 2001-162384, filed on May 30, 2001, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, in particular, to a low on-resistance power MOSFET or an insulated gate field effect transistor that is used in an IC exhibiting high breakdown voltage and controlling high current, for example, an IC in a switching regulator, an IC for driving an automobile electric power system, or an IC for driving a flat panel display. The present invention also relates to a method for manufacturing such a semiconductor device.
2. Description of the Related Art
The importance of power ICs containing a power MOSFET has been increasing with the rapid spread of portable apparatuses and advancements of communications technology in recent years. A power IC integrating a lateral power MOSFET with a control circuit is expected to achieve miniaturization, low power consumption, high reliability, and low cost in comparison with a conventional construction combining a discrete power MOSFET with a controlling and driving circuit. Consequently, developmental work is actively being conducted for high performance lateral power MOSFETs based on CMOS processes.
FIG. 13 is a cross sectional view showing a structure of a conventional lateral power MOSFET for a withstand voltage of 30 V. This lateral power MOSFET 101 includes pxe2x88x92 well 11, gate oxide film 12, gate electrode 13, source electrode 14, and drain electrode 15 that are formed on a pxe2x88x92 substrate 10. The lateral power MOSFET 101 further includes p diffusion region 16, n+ diffusion region 17, nxe2x88x92 drift region 18, and n+ diffusion region 19 formed in the surface region of the pxe2x88x92 well 411 arranged laterally.
This type of lateral power MOSFET is limited in miniaturization because an extended drain formed on the surface region of the substrate to ensure a withstand voltage. A punch through voltage also limits the miniaturization since a channel is formed in the direction parallel to the substrate surface in this type of MOSFET. Because the drift region 18 and the channel are formed in parallel with the substrate surface, density of integrated devices cannot be raised. Therefore, the channel width per unit area cannot be increased. Thereby, restricting reduction of on-resistance per unit area.
A large number of reports have been made on lateral power MOSFETs. For example, a paper entitled xe2x80x9cA 0.35 xcexcm CMOS based smart power technology for 7 V-50 V applications,xe2x80x9d in Proceedings of ISPSD 2000 by V. Parthasarathy et al., discloses a lateral power MOSFET that exhibits the breakdown voltage of 44 V and on-resistance per unit area of 30 mxcexa9-mm2. A device pitch is estimated to be 3.6 xcexcm in the case of 0.35 xcexcm rule, where the device pitch is a distance from the source center to the drain center, that is the sum of lengths L11, L12, L13 and L14 shown in FIG. 13. When a required withstand voltage increases, the drift region becomes larger, resulting in larger device pitch.
A MOSFET having a trench structure for reducing the device pitch and enhancing degree of integration of a device is known. Rather, the inventor of the present invention has proposed a lateral power MOSFET employing a trench structure (hereinafter referred to as xe2x80x9ca trench lateral power MOSFETxe2x80x9d) in the paper entitled xe2x80x9cA trench lateral power MOSFET using self-aligned trench bottom contact holesxe2x80x9d in IEDM ""97 Digest, p. 359-362, 1997. FIGS. 14 through 16 show the structure of the trench lateral power MOSFET. FIG. 14 is a plan view. FIG. 15 is a cross-sectional view along the line Axe2x80x94A of FIG. 14 and shows the structure of an active region where electric current is driven as a MOSFET operation.
FIG. 16 is a cross-sectional view along the line Bxe2x80x94B of FIG. 14 and shows the structure of a gate region where gate polysilicon is lead out to the substrate surface.
This MOSFET 102 includes a gate oxide film 22 formed on an inner wall of a trench 21 that is formed in a pxe2x88x92 substrate 20, gate polysilicon 23 formed inside a gate oxide film 22, a drain region 29 that is an n+ diffusion region is formed at a bottom of the trench 21, and a source region 27 that is an n+ diffusion region is formed at the outer periphery of the trench 21. The drain region 29 is surrounded by an nxe2x88x92 drain region 28 that is an nxe2x88x92 diffusion region surrounding the lower portion of the trench 21. The nxe2x88x92 drain region 28 is surrounded by a p body region 31 that is a pxe2x88x92 diffusion region.
A p+ diffusion region 32 is formed outside the source region 27, and a p base region 33 is formed under the source region 27. A thick oxide film 34 is provided in the lower portion of the trench 21 to ensure a withstand voltage. In FIGS. 14 through 16, symbol 24 represents a source electrode, symbol 25 a drain electrode, symbol 26 an interlayer oxide film, symbol 35 a gate electrode, symbols 36 and 37 contact parts, symbol 38 an n+ diffusion region, and symbols 39 and 40 represent interlayer oxide films. The on-resistance per unit area of the trench lateral power MOSFET 102 with the breakdown voltage of 80 V is 80 mxcexa9-mm2. The device pitch is 4 xcexcm, which is about half the device pitch of a conventional lateral power MOSFET with a breakdown voltage of 80 V.
In a lateral power MOSFET with a withstand voltage lower than 80 V, say 30 V, it is desirable to reduce the device pitch. However, since the trench lateral power MOSFET 102, as shown in FIGS. 14 through 16, is suitable for the withstand voltage of 80 V, it is inexpedient to apply the same structure to a MOSFET with a withstand voltage lower than 80 V. Specifically, the thick oxide film 34 for securing a withstand voltage in a MOSFET with a withstand voltage lower than 80 V may be thinner than the thickness in a MOSFET for the withstand voltage of 80 V. Accordingly, an overall size of the MOSFET can be reduced if the thickness of this oxide film 34 is reduced to the minimum required dimension for the withstand voltage lower than 80 V. On the contrary, if the same structure as the device for the withstand voltage of 80 V is applied, the overall size of the device becomes larger than a device in which the thickness of the oxide film 34 for ensuring that a withstand voltage is optimized. As a result, poor performances occur, e.g., larger wiring resistance around the semiconductor element.
The area of the gate is also excessively large, in comparison with the case in which the thickness of the oxide film 34 is optimized. As a result, parasitic capacity of the gate increases and driving losses increase. In a manufacturing process of the trench lateral power MOSFET 102, a shallow trench is first dug. After protecting the side wall of the trench with a nitride film, a deep trench is dug and then, thermally oxidized to form the thick oxide film 34. Thus, the manufacturing process is rather complicated, which may result in a lowering of yield rate.
The present invention has been made in view of the above problems, with an object of the invention being to provide a semiconductor device making a trench lateral MOSFET that can be manufactured by a process simpler than the process for a conventional trench lateral power MOSFET with a withstand voltage of 80 V class, and is optimized for a withstand voltage lower than 80 V so as to have a device pitch smaller than that of a conventional lateral power MOSFET with a withstand voltage lower than 80 V, and to exhibit low on-resistance per unit area.
Another object of the present invention is to provide a method for manufacturing such a trench lateral MOSFET.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
To attain the above objects, a semiconductor device of an embodiment of the present invention includes trenches that are formed shallow and narrow with a short pitch in a semiconductor substrate, a drift region formed around the trench, a gate insulating film having a uniform thickness of about 0.05 xcexcm, for example, formed on the inner wall of the trench, gate polysilicon formed inside the gate insulating film, a base region and a source region formed in the surface region of the substrate, a drain region formed at the trench bottom, interlayer dielectric provided inside the gate polysilicon, and drain polysilicon filling a space inside the interlayer dielectric and electrically connecting to the drain region.
According to another an embodiment of the present invention, a channel region, which needs a certain distance for achieving high breakdown voltage, is formed vertically along the side wall of the trench. The drift region formed at the trench bottom corresponding to a thickness of the interlayer dielectric has a function to relax the electric field of this region. The regions required by the device pitch are only a source contact region and a drain contact region. Because a MOSFET is formed by means of self-aligning at the side wall region of the trench, precise mask alignment is not necessary. A thick oxide film for ensuring a high withstand voltage is also unnecessary unlike a conventional trench lateral power MOSFET for a withstand voltage of 80 V. Trench etching may only need to be conducted once in the manufacturing process of this embodiment of the present invention.